The present invention relates generally to synchronous memory controllers, and, more particularly, to a buffer and control circuit for a synchronous memory controller.
Synchronous memory controllers facilitate communication between microprocessors and synchronous memories, viz., double-data rate synchronous random dynamic access memories (DDR-SDRAMs). Due to the synchronous nature of storage, a bi-directional reference signal (commonly referred to as a DQS signal) is used to synchronize the states of the memory controller and the memory during data transfer. Buffer and control circuits are used as interfaces between the memory controller and the memory; each of the two devices has an integrated buffer and control circuit. Communication signals between the two devices pass through respective buffer and control circuits.
Communication between the memory controller and the memory primarily involves read/write operations. During a read operation, data is transmitted from the memory and captured by the memory controller. The read operation is preceded by transmission of the DQS signal from the memory buffer and control circuit to the controller buffer and control circuit. The memory uses the DQS signal to apprise the memory controller of an impending read operation. Thereafter, the controller buffer and control circuit generates a reference strobe signal based on the DQS signal and used by the memory controller to determine exact time instants of beginning and ending of various stages of the read operation.
FIG. 1 illustrates a conventional buffer and control circuit 100. The buffer and control circuit 100 includes first and second differential comparators 102a and 102b, control logic 104, and first and second offset circuits 106a and 106b. 
The DQS(+) and DQS(−) signals are transmitted by a synchronous memory (not shown) to communicate the start and end of various stages of a read operation to a synchronous memory controller. Industry standards define multiple states of the DQS(+) and DQS(−) signals to indicate the start and end of various stages during the read operation. For example, before the read operation begins, the DQS(+) and DQS(−) signals are in a high impedance state and voltages of the DQS(+) and DQS(−) signals remain at undefined levels between logic high and low states. To signal a beginning of the read operation, the DQS+ signal is driven from the high impedance state to logic low state. Simultaneously, the DQS− signal is driven from the high impedance state to logic high state. The DQS(+) and DQS(−) signals are transmitted to the positive and negative input terminals of the first differential comparator 102a, respectively. The first differential comparator 102a receives first and second supply voltages V1 and V2. The first differential comparator 102a generates a DQS_IN signal that is high when difference between the DQS(+) and DQS(−) signals is above a predetermined threshold. Similarly, the DQS_IN signal is low when this difference is less than the predetermined threshold. Thus, the DQS_IN signal indicates the beginning and ending of the read operation.
The DQS(+) and DQS(−) signals also are provided to the first and second offset circuits 106a and 106b. The first offset circuit 106a provides a negative offset to the DQS− signal and the second offset circuit 106b provides a positive offset to the DQS+ signal. The offset DQS(+) and DQS(−) signals are provided to positive and negative input terminals of the second differential comparator 102b, respectively. The second differential comparator 102b receives the first and second supply voltages V1 and V2. The second differential comparator 102b compares the offset DQS(+) and DQS(−) signals and generates a logic high signal when the difference is above the predetermined threshold and generates a logic low signal when the difference is less than the predetermined threshold. Thus, offsetting the DQS(+) and DQS(−) signals enables detection of divergence and convergence in the magnitudes of the DQS(+) and DQS(−) signals only when the DQS(+) and DQS(−) signals have been driven substantially apart (to signal start of data transfer) or substantially close (to signal end of data transfer). Therefore, the output of the second differential comparator 102b is referred to as a separation signal, DQS_SEP_IN.
The DQS_IN and DQS_SEP_IN signals are provided to the control logic 104. The control logic 104 gates and enables the DQS_IN signal based on the DQS_SEP_IN signal to generate a reference strobe signal, DQS_Digital_In. Thus, the DQS_Digital_In is driven high upon indication of a valid transmission of the data by the memory. The DQS_Digital_In signal is transmitted to the memory controller, which is then set ready to capture data transmitted from the memory.
The DQS_Digital_In signal must accurately represent the detected stage of the read operation (by the first and second differential comparators 102a and 102b). A corrupt DQS_Digital_In signal will lead to capturing inaccurate data. Therefore, it would be advantageous to have a robust buffer and control circuit that eliminates data capture faults and allows seamless transmission of data in to a memory controller, and that overcomes the above-mentioned limitations of conventional buffer and control circuits.